1. Field of the Invention
The present invention relates to semiconductor devices, in particular to a transistor and a diode, each having a structure in which semiconductor crystal is epitaxially grown.
2. Description of the Related Art
FIG. 32 is a sectional view of a conventional transistor 101, showing a cross section of a processed substrate taken along a plane across a source region described below and parallel to a surface of the substrate. FIG. 33(a) is a sectional view taken along the line X—X in FIG. 32, and FIG. 33(b) is a sectional view taken along the line Y—Y in FIG. 32.
This transistor 101 is a trench type power MOSFET including a single crystal substrate 111 and a drain layer 112. The single crystal substrate 111 is made of silicon single crystal doped with an N+-type impurity at a high concentration. The drain layer 112 is made of an N−-type silicon epitaxial layer that is formed by epitaxial growth on the single crystal substrate 111. The reference numeral 110 denotes a processed substrate having the single crystal substrate 111 and the drain layer 112.
The surface of the processed substrate 110 is etched so that rectangular ring-shaped hole is formed thereon.
P-type base region 133 is formed on the surface of the processed substrate 110 inside the inner circumference of the ring-shaped hole. In the vicinity of the surfaces within the base region 133, a plurality of P+-type ohmic regions 165, and N+-type source regions 166 are respectively formed.
At the position between the source regions 166, the surface of the processed substrate 110 is etched strip shape to form narrow grooves.
On the bottoms of the narrow grooves and the above-described ring-shaped hole, buried portions 126a and 126b made of a semiconductor filler having an opposite conductivity type to that of the drain layer 112 are respectively formed. An upper end of each of the buried portions 126a and 126b is situated below the boundary between the base region 133 and the drain layer 112. The formation of the buried portions 126a and 126b make the depths of the narrow grooves and the ring-shaped hole shallow, respectively.
A gate insulating film 157 is formed on the inner surface of each of the narrow grooves and the ring-shaped hole now having a shallow depth. The narrow grooves and the ring-shaped hole is filled with polysilicon while polysilicon is being insulated from the processed substrate 110 by the gate insulating films 157. Gate electrode plugs 155a and 155b are formed by the thus filling polysilicon, respectively.
The gate electrode plugs 155a and 155b are connected to each other through a gate electrode film made of a metal thin film not shown in the drawing.
On the surfaces of the source regions 166 and the ohmic regions 165, a source electrode film 167 made of a metal thin film is formed. Interlayer insulating films 163 are formed on the gate electrode plugs 155a and 155b. The interlayer insulating films 163 electrically insulate the source electrode film 167 and the gate electrode plugs 155a and 155b from each other.
A plurality of rectangular ring-shaped guard ring portions 1251 to 1253 are provided in a region outside the ring-shaped hole provided on the processed substrate 110. Each of the guard ring portions 1251 to 1253 is formed by diffusion of a p-type impurity having an opposite conductivity type to that of the drain layer 112 into the surface of the processed substrate 110. The guard ring portions 1251 to 1253 are concentrically provided.
On the back surface of the processed substrate 110, i.e. on the surface of the single crystal substrate 111, a drain electrode film 170 is formed.
In the thus formed transistor 101, the source electrode film 167 is connected to a ground potential while a positive voltage is applied to the drain electrode film 170. In such a state, a positive voltage equal to or higher than a threshold voltage is applied to each of the gate electrode plugs 155a and 155b, an n-type inversion layer is formed in a channel region (corresponding to an interface between the base region 133 and the gate insulating film 157). Then, the source regions 166 and the drain layer 112 are connected to each other through the inversion layer, so that a current is allowed to flow from the drain layer 112 to the source regions 166. In such a condition, the transistor 101 is in a conductive state.
When the potential of each of the gate electrode plugs 155a and 155b is put at the same potential as a source potential in such a state, the inversion layer disappears so that current is not passed. In this condition, the transistor 101 is in a cutoff state.
In the state where the transistor 101 is in a cutoff state and a large voltage is applied between the drain electrode film 170 and the source electrode film 167, PN junctions formed between the base regions 133 and the drain layer 112 are reverse biased, a depletion layer expanded into the p-type base regions 133 and the n-type drain layer 112. When edges of the expanded depletion layer are in contact with the buried portions 126a and 126b placed below the respective gate electrode plugs 155a and 155b and the respective guard ring-shaped portions 1251 to 1253, the base regions 133 and the buried portions 126a and 126b are connected to each other through the depletion layer. At the same time, the base regions 133 and the guard ring-shaped portions 1251 to 1253 are connected to each other through the depletion layer. In this manner, the potential of each of the buried portions 126a and 126b and the guard ring-shaped portions 1251 to 1253, which has been at a floating potential, is stabilized. As a result, the depletion layer is also expanded into the drain layer 112 from each of the buried portions 126a and 126b and the guard ring-shaped portions 1251 to 1253.
Each of the guard ring-shaped portions 1251 to 1253 is formed by diffusion. Therefore, if each of the guard ring-shaped portions 1251 to 1253 is intended to be deeply formed so as to increase a withstanding voltage, its width is also correspondingly increased. As a result, the area of an element is increased.
On the other hand, if each of the guard ring-shaped portions 1251 to 1253 is formed shallowly, breakdown occurs not at the PN junction between each of the buried portions 126a and 126b and the drain layer 112 but at the PN junction between each of the guard ring-shaped portions 1251 to 1253 and the drain layer 112 when a reverse bias at a high voltage is applied thereon.
Since the area of the PN junction between each of the guard ring-shaped portions 1251 to 1253 and the drain layer 112 is smaller than that of the PN junction between each of the buried portions 126a and 126b and the drain layer 112, there arises a problem in that a breakdown current flowing through such a small area is likely to break down an element.